A ferroelectric material exhibits polarization when an external electric field is applied, and maintains the polarization even after removing the external electric field. Also, the ferroelectric material is a material that may control a direction of spontaneous polarization with a change of the electric field. The ferroelectric material includes PZT[Pb(Zr, Ti)O3], SBT[SrBi2Ta2O9] and the like. The said characteristics of the ferroelectric material may be used to form binary memory devices. Therefore, extensive studies for applications of a ferroelectric random access memory (FRAM) have been progressed.
Generally, a FRAM device has a planar capacitor structure comprising planar upper and lower electrodes, and a ferroelectric thin layer between the electrodes. The upper and lower electrodes are made of noble metals such as iridium or platinum or their oxides. The ferroelectric thin layer is made of a ferroelectric material that is formed by a sol-gel method, sputtering, or chemical vapor deposition (CVD). However, as an integration level of a semiconductor memory device increases, a cell area of the FRAM device decreases. Hence, the capacitor area included in the cell is also becoming gradually reduced. Therefore, to ensure a sufficient capacitance, the capacitor structure needs to be three-dimensional so that the surface area of the capacitor may be increased. But, to form such a three-dimensional capacitor, additional steps should be taken in a conventional fabricating method. Since the additional steps may add significant cost in fabricating the semiconductor device, the number thereof is preferably minimized.
In a DRAM having a similar structure to a FRAM, a capacitor over bit line (COB) capacitor including both a storage node contact and a capacitor lower electrode may be employed. Unlike the DRAM, however, it is not preferable that both the storage node contact and the capacitor lower electrode belong to the FRAM capacitor with electrodes made of the noble metal. This is because an amount of the noble metal is preferably minimized to reduce the fabrication costs of the semiconductor device. In addition, some electrode materials are not preferable as the storage node contact due to a high electrical resistance or a poor gap fill characteristic.
In another approach, to increase the area of the lower electrode, a cylinder-type COB capacitor may be used. In this case, however, a node separation process of the lower electrode is not easily performed using chemical mechanical polishing (CMP). In addition, the cylinder is hardly formed when the lower electrode material suffers from degradation of a step coverage characteristic. For this reason, the cylinder-type COB capacitor also is not suitable for the FRAM device.
In addition, the capacitor of a stacked structure is also improper to the FRAM device. Forming of the capacitor of the stacked structure comprises stacking a thick lower electrode on the contact plug, then patterning the resultant structure where the lower electrode is stacked. In this method, since most of a high-priced material constituting the lower electrode layer is removed, the fabrication costs may be increased. Also, an etch process for forming the lower electrode is not easily performed.
FIG. 1 shows a method of fabricating a three-dimensional FRAM capacitor while minimizing the above-mentioned problems.
Referring to FIG. 1, a contact plug is formed as known to those skilled in the art. A lower interlayer insulating layer 12 is formed on a substrate 10. A lower contact plug 14 is formed to penetrate the lower interlayer insulating layer 12. An upper contact plug 18 is formed to be in contact with the lower contact plug 14. Forming the upper contact plug 18 comprises forming an upper interlayer insulating layer (not shown) on an entire surface of the semiconductor substrate where the lower contact plug 14 is formed. The upper interlayer insulating layer is then patterned to form an upper contact hole exposing the lower contact plug 14. The upper contact plug 18 is formed to fill the upper contact hole. Thereafter, the upper interlayer insulating layer is removed to expose both the upper contact plug 18 and the lower interlayer insulating layer 12.
Continuously, a lower electrode 22, a ferroelectric layer pattern 24, and an upper electrode 26 sequentially cover the exposed upper contact plug 18 to form a capacitor 20. In these steps, the upper contact plug 18 is exposed on the lower interlayer insulating layer 12, thereby forming the three-dimensional lower electrode 22. As a result, a capacitance of the capacitor may be increased. Examples of the foregoing conventional method are disclosed in U.S. Pat. No. 5,581,436, U.S. Pat. No. 5,499,207, and U.S. Pat. No. 6,043,526.
However, even in the conventional method, additional steps should be taken to make the structure of the upper contact plug three-dimensional. That is, the method should further comprise stacking, patterning, and removing the upper interlayer insulating layer. In addition, as the integration level of the semiconductor device increases, a margin of an exposure process is gradually reduced. Therefore, a likelihood of a misalignment is gradually increased while patterning the upper interlayer insulating layer. The misalignment may cause a decrease in a contact area between the upper and lower contact plugs.